Question $3$: Memory Access Time

$($a$)$ Given the following information compute the total time for all memory accesses and the AMAT for both the caches.

There is$,$ separate instruction and data cache.

Program contains $40$ instructions out of which $8$ instructions are load$/$store instructions.

Instruction Cache Miss rate is $7\mathrm{.}5\%$ and Data Cache Miss rate is $10\%.$

Processor CPI is $1\mathrm{.}5.$

Miss penalty is $80$ clock cycles.

Clock Speed is $4GHz.$

$($b$)$ Given the following information compute the AMAT for memory accesses.

There are two levels of caches $-L1$ and $L2.$

Program contains $40$ instructions out of which $8$ instructions are not available in $L1$ cache.

$4$ of the instructions can be accessed from $L2$ cache, while the remaining need to be accessed from Main Memory.

Processor CPI is $1\mathrm{.}5$ and L$2$ access time is $5$ clock cycles.

Miss penalty is $80$ clock cycles.

Clock Speed is $4GHz.$