Question: this is for bonus points and the objective is to use vector inputs and outputs with the when else VHDL statement instead of using individual


this is for bonus points and the objective is to use vector inputs and outputs with the "when else" VHDL statement instead of using individual and simplified SOP statements but i cant figure out the first thing about when else. Also this was done in vivado 2017.2.
CG =(((NOT A) AND (NOT B) AND (NOT C)) OR (A AND B AND (NOT C) AND (NOT D)) OR ((NOT A) AND B AND C AND D)); CF =((NOT A) AND (NOT B) AND D) OR ( (NOT A) AND C AND D) OR ((NOT A) AND (NOT B) AND C) OR (A AND B AND (NOT C) AND D); CE((NOT A) AND D) OR ((NOT A) AND B AND (NOT C)) OR ((NOT B) AND (NOT C) AND D) ; CD=(B AND C AND D) OR ( (NOT A) AND B AND (NOT C) AND (NOT D)) OR ((NOT A) AND (NOT B) AND (NOT C) AND D) OR (A AND (NOT B) AND C AND (NOT D)); CC =(A AND B AND C) OR (A AND B AND (NOT D)) OR ((NOT A) AND (NOT B) AND C AND (NOT D)); CB(A AND C AND D) OR (B AND C AND (NOT D)) OR (A AND B AND (NOT D)) OR ((NOT A) AND B AND (NOT C) AND D) ; CA
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