Question: A CPU has a 6 4 KB mapped cache with 1 2 8 - byte block size. Suppose A is a two dimensional array of

A CPU has a 64KB mapped cache with 128-byte block size. Suppose A is a two
dimensional array of size 512\times 512 with elements that occupy 8-bytes each. Consider the following
two code segments, P1 and P2. P1 and P2 are executed independently with the same initial state,
namely, the array A is not in the cache and i,j,x are in registers. Let the number of cache misses
by P1 be M1 and the number of cache misses by P2 be M2.
P1
for (i =0; i <512; i++){
for (j =0; j <512; j++){
x += A[i][j]
}
}
P2
for (i =0; i <512; i++){
for (j =0; j <512; j++){
x += A[j][i]
}
2
}
Calculate the value of M1/M2
.

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