This problem is intended to be solved using Jade simulator. Please show a drawn out circuit diagram $($ex$.$ using and, or$,$ nor, not gates...$)$NOT CODE. Design an adder'subtractor $($ARITH$)$ unit that operates on $32-$blt 'two's complement' $($see the

note in the box below$)$ inputs and generates a $32-$blt output. It will be useful to generate three

other culput signals to be used by the CMP unit: $Z$ which is true when the $S$ putputs are all zero,

$$ which is true when the addition operation overflows $($i$.$e$.,$ the result is top large to be

represented in $32$ bits$),$ and $N$ which is true when the sum is negative $($i$.$e$.,S[31]=1).$ Overfow

can never occur when the two operands to the addition have different signs; if the two operands

have the same sign, then overfow can be detected if the sign of the result differs from the sign

of the coerands:

$V=x{A}_{31}*x{B}_{31}\frac{*}{b}ar(S_{31})\frac{+}{b}ar(x{A}_{31})\frac{*}{b}ar(x{B}_{31})*S_{31}$

Note that this equation uses XB$[31],$ which is the high$-$order bit of the $B$ operand to the adder

itself $($i$.$e$.,$ after the XOR gate $-$ see the schematic below$).$ XA$[31]$ is simply A$[31].$

Note on "Two's Complement": Our ARITH unit uses 'two's complement' representations of

the binary numbers, in order to be able to represent both posittive and negat$/$ve numbers in the

mathematical copations it periorms. In two's complement, the first bit of a binary number lets

you know if the number is positive $($in which case that first bit is $$@ $"),$ or negative $($in which

case the first bit is $"1").$ In our $32-$bit ARITH unit, this first bit is S$[31].$ There are some other

subtleties to how two's complement encodes negative numbers, but those should not affect

your design in this assignment.

The following schematic is one suggestion for how to $90$ about the design:

AFN will be set to $0$ for en ADD $(S=A+B)$ and $1$ for a SUBTRACT $(S=A-B)$; $]$ and

$B[31$:$0]$ are the $32-$bit two's complement input operands; $S[31$:$0]$ is the $32-$bit result, $\frac{Z}{N}\frac{?}{N}$ are

the three condition code bits described above. We'll be using a bit numbering convention where

bit $31$ is the most$-$significant bit and bit $0$ is the lesst$-$significant bit $($this is called "little$-$endian"$).$

We've provided a FA moclule for entering the gate$-$level schematic for the full adder lilike the one

you built in Discussion 'DIS$2$: Architectural Simulation Touls'$)$ to be used in constructing the

$32-$bit ripple carry adder that forms the heart of the ARITH unit.

The AFN input signal selects whether the operation is an ADD or SUBTRACT. To do a

SUBTRACT, the circuit first computes the two's complement negation of the B operand by

inverting $B$ and then adding one $($which can be done by forcing the carry$-$in of the $32-$bit add to

be $1).$ Start by implementing the $32-$bit add using a ripple$-$carry architecture $\{$again$,$ like the one

from Discussion DIS$2).$ You'll have to construct the $32-$input NOR gate required to compute Z

using a tree of smaller fan$-$in gates $($the parts library only has gates with up to $4$ inputs$).$

When entering your circuitry, remember to delete the original jumpers and wires that connected

the outputs to ground

The module test tries adding and subtracting various operands, ensuring that the $Z,V$ and $N$

outputs are correct after each operation.