This question concerns software interlocking to resolve read$-$after$-$write hazards in

pipelined CPU execution. Consider an ARM $5-$stage pipeline with no forwarding and

hazard detection. How many NOPS should be inserted in the following instruction

sequence so all hazard are eliminated?

a$.2$ between I and I,$1$ between $I3$ and $I4,2$ between I and $I5$

b$.2$ between I and I,$2$ between $I3$ and $I4,1$ between $I4$ and $I5$

c$.1$ between $I1$ and I,$1$ between $I3$ and $I4,1$ between $I4$ and $I5$

d$.2$ between $I1$ and I,$1$ between I$3$ and I$4,1$ between I$4$ and I$5$

e$.1$ between I and $I2,2$ between $I3$ and $I4,2$ between $I4$ and $I5$