This table describes a state machine for use in $6\mathrm{.}1$ and $6\mathrm{.}2.$

$6\mathrm{.}1$ Implement as a One$-$Hot state machine $($OR gates, AND gates, state bit registers$).$ States A$,$

$B,C,D=4^{\text{'}}b1000,4^{\text{'}}b0100,4^{\text{'}}b0010,$ and $4^{\text{'}}b0001,$ respectively. Reduce$/$optimize transition

logic & output logic. Please write a Boolean or Verilog equation for each state bit. $(20$ points$)$

NextState$[3]($for StateA$)$:

NextState$[2]($for StateB$)$:

NextState$[1]($for StateC$)$: