To add k N-bit words, you need k-1 N-bit adder. For example, to add 0001 + 0111 + 1101 + 0010 = 10111 you need a structure similar the one shown below (a). Classical full adder sums 3 inputs to produce 2 outputs: Carry (C) and Sum (S) where the C has twice the weight of the sum output. If you design N full adder in parallel shown in (b), then this produces N Sums and N Carry outs. This is called Carry Save Adder (CSA). To add N-bit words, a 2-stage of CSA followed by a regular adder as shown. In this structure, the carry bits are logically shifted by one bit after each stage to reflect the weight The size of the of the carry. CSA is increased by a single bit at the next stage. At the last stage, the carry propagation is performed. 1011 S 0101 C 0101 0001 0111 1101 0010 X Y Z XY, Z, X Y Z X, Y, Z, 0001 X 0001 0111 1101 0010. 0111 Y +1101 Z 4-bit CSA 0101 1011 CS C S3 XYZN C S C, S 5-bit CSA 1011 Y +0010 Z 01010 00011 00011 S n-bit CSA 01010 C 10101 + 10111 CN 1 SN 1 (b) (a) 10111 (c) 01010 A + 00011 B 10111 S a) Design a CSA in Verilog to add a sequence of 10 8-bit binary numbers. How many CSA stages are needed (explain). b) Use Modelsim to simulate your design with the following sequence: (11, 2,13,4,5,6,7,8,9,10) and (3,14,5,6,7,8,19,10).