To design, simulate, synthesize, and implement a 4-bit Super-Register with a 3-bit control input A. The register operates according to the following table:

A Action 000 Hold State 001 Shift Left 010 Shift Right 011 Synchronous Clear 100 Synchronous Preset 101 Count Up 110 Count Down 111 Load

The register also has a 4-bit output (Q), a 4-bit input (D), a synchronous clock input, a Right-Shift-In input (RSI), and a Left-Shift-In input (LSI). Use delayed flip-flop and 8- to-1 multiplexer to design 4-bit Super-Register.