Transmission Vectored Bit: A $4-$Bit Parity Vector $($P$1-$P$4)$ are interlaced with the $8-$bit

Data Vector $($D$1$:D$8)$ and an additional parity bit P$5$ is appended to the $12-$bit hamming

code to ensure that the entire $13-$bit vector is even parity:

P$1$ P$2$ D$1$ P$3$ D$2$ D$3$ D$4$ P$4$ D$5$ D$6$ D$7$ D$8$P$5$

$1)$ Create an ECC Generator, at the I$/$O Controller from the $8-$bit Data Vector. The

output of the ECC Generator will be the $13-$Bit Vector.

$2)$ Construct a $13-$bit Data Transmission bus to send the $8-$bit binary data and $5$ parity

bits over to Memory.

Hex Displays Memory I$/$O Controller

$2$

$3)$ Construct an ECC Detector at Main Memory that corrects for single bit errors.

Generally an interrupt$/$error handler is used to handle errors from the OS$,$ for this exercise

we will use $3$ Hex displays, $2$ for data and $1$ for an error status, for diagnostic purposes:

$.$ In the event that no error has occurred, your design must display the data transferred

using the $2$ Hex data displays and a $0$ as an error status.

$.$ For single bit transmission errors, your system must correct the error and display the

data along with $$C$$ in the $3$rd Hex Display.

$.$ For $2-$bit transmission errors, your design must display $$E$$ in the error status display.

$4)$ Make sure that the ECC Generator, the Data Transmission bus, and the ECC Detector

are completely connected.