Two alternative cache designs for a processor are considered, one with a unified cache of $256$

KB and the other with a split cache of $128$ KB I$-$cache and $256$ KB D$-$cache. The misses per

$1000$ instructions for I$-$cache, D$-$cache and Unified cache are $0\mathrm{.}30,35\mathrm{.}3,$ and $32\mathrm{.}9,$ respectively.

Which cache design has the lower miss rate? Assume that $36\%$ of the instructions are data

transfer instructions, the hit takes two clock cycles, the miss penalty is $200$ clock cycles, and

the load or store hit takes one extra clock cycle on a unified cache