Question: { USE GATE MODELING } ' ' ' ' DO NOT USE ASSIGN and ALWAYS Objective: To implement a Verilog gate level model for 3

{USE GATE MODELING}
''''DO NOT USE ASSIGN and ALWAYS
Objective: To implement a Verilog gate level model for 32-bit register.
Outcome:Gate level implementation for the following components.
SR_LATCHD_LATCHD_FFREG1REG32
Instruction: Complete gate level description offollowing components in logic.v file.
SR_LATCHD_LATCH D_FFREG1REG32
Compile entire Project03and simulate following modules inModelSim simulator.
SR_LATCH_TBD_LATCH_TBD_FF_TBREG1_TBREG32_TB
Observe corresponding outcomeson waveform windows and fix any issue.
Each testbench will generate corresponding output file.
OUTPUT/sr_latch_tb.outOUTPUT/d_latch_tb.outOUTPUT/d_ff_tb.outOUTPUT/d_reg1_tb.outOUTPUT/d_reg32_tb.out
//32-bit registere +ve edge, Reset on RESET=0
module REG32(Q,D,LOAD, CLK,RESET);
output [31:0]Q;
input CLK,LOAD;
input [31:0]D;
input RESET;
//TBD
endmodule
//1bit register +ve edge,
//Preset on nP=0,nR=1,reset on nP=1,nR=0;
//Undefined nP=0,nR=0
//normal operation nP=1,nR=1
module REG1(Q,Qbar, D,L,C,nP,nR);
input D,C,L;
input nP,nR;
output Q,Qbar;
//TBD
endmodule
//1bit flipflop +ve edge,
//Preset on nP=0,nR=1,reset on nP=1,nR=0;
//Undefined nP=0,nR=0
//normal operation nP=1,nR=1
module D_FF(Q,Qbar, D,C,nP,nR);
input D,C;
input nP,nR;
output Q,Qbar;
//TBD
endmodule
//1bit D latch
//Preset on nP=0,nR=1,reset on nP=1,nR=0;
//Undefined nP=0,nR=0
//normal operation nP=1,nR=1
module D_LATCH(Q,Qbar, D,C,nP,nR);
input D,C;
input nP,nR;
output Q,Qbar;
//TBD
endmodule
//1bit SR latch
//Preset on nP=0,nR=1,reset on nP=1,nR=0;
//Undefined nP=0,nR=0
//normal operation nP=1,nR=1
module SR_LATCH(Q,Qbar, S,R,C,nP,nR);
input S,R,C;
input nP,nR;
output Q,Qbar;
//TBD
endmodule
// memory data file (do not edit the following line - required for mem load use)
// instance=/SR_LATCH_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000042
00000043
00000047
0000004b
0000004f
00000021
00000023
00000027
0000002b
0000002f
0000005b
00000053
00000037
00000033
// memory data file (do not edit the following line - required for mem load use)
// instance=/D_LATCH_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000022
00000023
00000027
00000011
00000013
00000017
0000002f
0000001b
// memory data file (do not edit the following line - required for mem load use)
// instance=/D_FF_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000012
00000013
0000000b
00000017
0000000d
0000000f
00000017
// memory data file (do not edit the following line - required for mem load use)
// instance=/REG1_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000022
00000023
0000000b
0000002f
0000001d
0000001f
00000023
// memory data file (do not edit the following line - required for mem load use)
// instance=/REG32_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
00000000
a5a5a5a5
ffff0000
00000000
00000000
0000ffff
0000ffff

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