Use System Verilog to design a module that performs one of four operations on two 4-bit inputs to produce one 4-bit output as specified below. Use always and clase statements, and begin - end statements if needed. Include explanatory comments in the module's System Verilog code as needed. Inputs Outputs a[3:0), b[3:0), s(1:0) y(3:0) function 0 y = a +b, unsigned add Function y = a