Use the code shown below to complete all the sub$-$parts of this problem

add x$1,$ x$0,$ x$0$ ; zero register

addi x$2,$ x$1,10$ ; set counter $($lcv$)$

addi x$5,$ x$0,2000$ ; get address of A$[]$s first element

Strt: ld x$7,0($x$5)$ ; get A$[$ i $]$

addi x$7,$ x$7,12$ ; update value

sd x$7,0($x$5)$ ; save A$[$ i $]$

addi x$5,$ x$5,8$ ; update array pointer

subi x$2,$ x$2,1$ ; decrement lcv

bne x$2,$ x$1,$ Strt ; loop again?

End: xor, x$4,$ x$1$

a$.$ Make the pipeline timing diagram for the "standard RISC$-$V pipe" for this code, running through the clock cycle that the second completion of sd occurs.

b$.$ Compute the speedup for the sequence in $($a$)$ over a non$-$pipelined run of the same sequence.

c$.$ Compute the CPI for the non$-$pipelined version when run on the sequence in $($a$).$

d$.$ Compute the CPI for the timing diagram case completed in $($a$).$

e$.$ List all dependencies in the code fragment shown above $($this part is not limited to the sequence shown in $($a$)).$ Show only first order ones $($i$.$e$.,$ no transitive$/$indirect ones!$).$ Write each one on a line by itself, recording line identifier, dependent register, and the instruction and register it depends on$,$ and the dependency type. For example, one entry might be:

Line $100,$ x$14$ depends Line $90\text{'}$s x$14,$ true data dependency.