Use the following RISC-V code where loads/stores and int operations take 1 cycle to execute, the FP multiplier takes 5 cycles and the FP adder takes 2 cycles, both FP units are pipelined. Unroll and schedule the code on a 2-issue superscalar as described below so that every cycle has at least one operation issued (no empty cycles). Fill the branch delay slot. Compute the CPI for each.

1. One pipeline handles all non-FP (loads/stores/integer operations, branches) operations, one handles all FP operations.
2. One pipeline can handle all operations, the other can handle non-FP operations.

Loop:

fld f1, 0(x1) // we are computing x[i+2] = x[i] + x[i+1] and

fld f2, 8(x1) // incrementing i by 3 in each iteration

fadd.d f3, f1, f2

fsd f3, 16(x1)

addiw x1, x1, 24

bne x1, x2, Loop