Using a JK$-$flip$-$flop derive$/$design a synchronous counter which will produce the following sequence; $1,2,3,6,7,1.$ Your solution should include the following; truth table, state transition k$-$maps, mappings to input JK flip$-$flop, circuit diagram and a timing diagram.

Pre Laboratory

Produce the following for your design;

truth table,

$[35$marks$]$

state transition k$-$maps,

mappings to input JK flip$-$flop,

Circuit diagram and a timing diagram.

$[5$marks$]$

I have one request. Please do not leave out the timing diagram and the simulation. Please do all the parts. Thank you I appreciate your help and work a lot Thank you