Using ModelSim, write the folllowing VHDL program:

Write a VHDL program consisting of a single entity whose architecture is a single

process that implements the following logic gate with 3 inputs and 1 output

inputs |output

a_in b_in c_in | result

0 0 0 0

0 1 0 1

1 0 0 1

1 1 0 0

0 0 1 0

0 1 1 0

1 0 1 0

1 1 1 1

Use exactly the names given above for the signals.

All your signals should be of type bit (NOT integer).