Write a VHDL program consisting of a single entity whose architecture is a single process that implements a programmable AND/OR gate. That is, a circuit which behaves like (a_in AND b_in) when control=1, but like (a_in OR b_in) when control=0 inputs |outputs a_in b in control | result 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | 1 Use exactly the names given above for the signals. Your process should not use the '+' symbol anywhere. All your signals should be of type bit (NOT integer).