Using Scheme in DrRacket please.

;Q3.1 ; enter your code here:

;Q3.2 ; enter your code here:

;Q3.3 ; enter your code here:

; Test cases (Display "half-adder Output ") (half-adder 0 0 0) (half-adder 0 0 1) (half-adder 0 1 0) (half-adder 0 1 1) (half-adder 1 0 0) (half-adder 1 0 1) (half-adder 1 1 0) (half-adder 1 1 1)

; Expected outputs ;0 ;1 ;1 ;0 ;1 ;0 ;0 ;1

; Test cases (Display "fullAdder Output ") (full-adder 0 0 0) (full-adder 0 0 1) (full-adder 0 1 0) (full-adder 0 1 1) (full-adder 1 0 0) (full-adder 1 0 1) (full-adder 1 1 0) (full-adder 1 1 1)

; Expected outputs ;(0 . 0) ;(0 . 1) ;(0 . 1) ;(1 . 0) ;(0 . 1) ;(1 . 0) ;(1 . 0) ;(1 . 1)

3 Define Scheme procedures to simulate the logic dezsign given in the diagram in Figure 3 . The procedures must follow the design in the figure and call the gate procedures that you defined in the previous questions and must return a pair with two elements ' (c . s), where s is the binary sum of a,b, and x (carry in), while c is the carry-out. You will implement the procedure in three steps using three procedures, as listed below. 3.1 Write a procedure (half-adder x a b) to generate (return) the sum bit s. The upper half of Fig. 3 that computes sum. 3.2 Write a procedure (carry-out x a b) to generate (return) the carryOut bit c. The lower half of Fig. 3. 3.3 Write a procedure (full-adder x a b) to generate the pair output (c.s), where s is the output of the half-adder procedure and c is the output of the carry-out procedure. A full-adder is also called a one-bit adder. Figure 3. The logic design of a one-bit full adder Verify your procedure by exhaustive testing: Use all valid inputs to test the procedure. There are eight valid inputs: (full-adder(full-adder(full-adder(full-adder(full-adder(full-adder(full-adder(full-adder00001111001100110)1)0)1)0)1)0)1) The test cases and expected outputs are given in the code template file. Do not remove or edit these lines