Using the DC operating conditions from the following table, give the noise margin LOW $($NML$)$ for the $74LS$ logic family.

$\backslash$table$[[\backslash$table$[[$Logic$],[$Family$]],$Year,DC Operating Condition,Speed $($MHz$)],[V_{Cc},V_{\text{O}\text{H}\text{m}\text{a}\text{x}},V_{\text{O}\text{H}\text{m}\text{i}\text{n}},$Volmax,Volmin,$V_{\text{i}\text{H}\text{m}\text{a}\text{x}},V_{\text{I}\text{H}\text{m}\text{i}\text{n}},V_{\text{I}\text{L}\text{m}\text{a}\text{x}},V_{\text{I}\text{L}\text{m}\text{i}\text{n}},$Icc,$I_{\text{m}\text{a}\text{x}(\frac{H}{L})}$