Using the LC4 Instruction Set table below, fill in the rest of this table convert the machine instructions to the equivalent sequence of assembly instructions.

LC4 Instruction Set table:

Address Example 0 1 2 3 4 Machine Instruction Assembly Instruction 0001001010000011 | ADD R1, R2, R3 1001000000000010 1001001000000011 0001010000100000 0010001100000001 0000110000000011 0001010010001000 0001001001111111 0000111111111011 5 6 7 Mnemonic Encoding NOP BRN IMM9 BREZ IMM9 BRnp IMM9 BRZ IMM9 BRzp IMM9 BRP IMM9 BRnZp IMM9 ADD Rd Rs Rt MUL Rd Rs Rt SUB Rd Rs Rt DIV Rd Rs Rt ADD Rd RS IMM5 CMP Rs Rt CMPU Rs Rt CMPI RS IMM7 CMPIU RS UIMM7 JSR IMM11 JSRR RS AND Rd Rs Rt NOT Rd Rs OR Rd RS RE XOR Rd Rs Rt AND Rd RS IMM5 LDR Rd RS IMM6 STR Rt RS IMM6 RTI CONST Rd IMM9 SLL Rd Rs UIMM4 SRA Rd Rs UIMM4 SRL Rd Rs UIMM4 MOD Rd RS RU JMPR RS JMP IMM11 HICONST Rd, UIMM8 TRAP UIMM8 LC4 Instruction Set Semantics Instructions Do Nothing N ? PC = PC+1+SEXT (IMM9) NIZ ? PC = PC+1+SEXT (IMM9) NIP ? PC = PC+1+SEXT (IMM9) Z ? PC = PC+1+SEXT (IMM9) ZIP ? PC = PC+1+SEXT (IMM9) P ? PC = PC+1+SEXT (IMM9) PC = PC+1+SEXT (IMM9) Rd = Rs + Rt Rd = Rs + Rt Rd = Rs - Rt Rd = Rs / Rt Rd = Rs + SEXT (IMM5) NZP = signed-CC (RS-Rt) NZP = unsigned-CC (Rs-Rt) NZP = signed-CC (RS-SEXT (IMM7)) NZP = unsigned-CC (RS-UIMM7) R7 = PC + 1; PC = (PC & 0x8000) 1 (IMM11 >> UIMM4 Rd = Rs >> UIMM4 Rd = Rs $ Rt PC = Rs PC = PC+1+SEXT (IMM11) Rd = (Rd & OxFF) (UIMM8 LC R1 .DATA . CODE . ADDR UIMM1 6 . FALIGN .FILL IMM16 .BLKW UIMM16 . CONST IMM16 .UCONST UIMM16 IIIIIIIIIIIIIIII 0000000000000000 001: opcode or sub-opcode ddd: d-register, sss: s-register, ttt: t-register III: signed immediate, UUU: unsigned immediate, --- don't care