Using the same MIPS code segment on a multi-cycle datapath processor: $ti, 0(s3) sub $a3, $t1, $a2 beq $t1, $t2, next addi $t2, t2, 1 and t3, $t2, $t1 next $t2, 4 (to) or $t3, Sa1, $a2 If the LW instruction begins in cycle 1, and the branch is NOT taken, in which cycle will a value be stored (written) into the $s3 register? If the LW instruction begins in cycle 1, and the branch is NOT taken, in which cycle will the ALU add 1 (decimal) to a register value? Using the same MIPS code segment on a multi-cycle datapath processor: $ti, 0(s3) sub $a3, $t1, $a2 beq $t1, $t2, next addi $t2, t2, 1 and t3, $t2, $t1 next $t2, 4 (to) or $t3, Sa1, $a2 If the LW instruction begins in cycle 1, and the branch is NOT taken, in which cycle will a value be stored (written) into the $s3 register? If the LW instruction begins in cycle 1, and the branch is NOT taken, in which cycle will the ALU add 1 (decimal) to a register value