Using verilog:

I have some starter code for a module that works. I want to split it up into three modules and instantiate.

Starter code:

I/Verilog behavioral model of a four-phase clock module FourPhaseClockVerilog ( /ame the module input Clock, Clear, //declare inputs output reg [0:3] P); //declare outputs as a register for convenience reg (1:0) state, nextstate; //declare internal state and next state variables parameter S0 = 2'600, S1 = 2'b01, S2 = 2'611, 53 = 2'b10; //parameterize states always @ (posedge Clock, negedge Clear) // watch for changes of Clock or Clear if (Clear == 0) state