Using Verilog's structural coding style, do the following: 1. Using Verilog's UDP coding style, write code for diff(A,B)>=2 knowing that A and B are binary numbers two bits each, that's it, A=a1a0,B=b1b0, the circuit has one output which is 1 when A and B are differ by 2 or more. 2. Using Verilog's UDP coding style, write code for 2 to 1 MUX 1 point 3. Write test bench for the entire module (MUX and diff)