Question: VAD to CPU Interrupt register (LSB) Disk R 10 Printer R 11 AL AL Priority encoder 0 Reader R 12 0 Keyboard R 0 13

VAD to CPU Interrupt register (LSB) Disk R 10 Printer R

VAD to CPU Interrupt register (LSB) Disk R 10 Printer R 11 AL AL Priority encoder 0 Reader R 12 0 Keyboard R 0 13 0 (MSB) IEN M IST Enable M M M Interrupt to CPU INTACK from CPU Mask register Consider the parallel priority interrupt hardware shown below. a. Suppose that the disk and printer sent interrupt requests to the CPU simultaneously. i. What is the content of the interrupt register (R3RzRtRo)? ii. What is the value (in decimal) of the vector address VAD? b. Suppose that the printer requests an interrupt. i. What is the content of the interrupt register (R3R2R-Ro)? ii. What is the value (in decimal) of the vector address VAD

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