VERILOG 4 Variable K-maps With case

Complete the Verilog implementation using only a case statement that provides the full truth table. The submission will be manually reviewed.

Complete a verilog module with the following header:

module test1( output logic y, input logic A,B,C,D ); 

that implements the following K-map:

C,D 00 01 11 10 01|1|0|0| 11 0 100