VERILOG 4 Variable K-maps With casez

Complete the Verilog implementation using only a casez statement that provides the implicates generated from the K-map.

Complete a verilog module with the following header:

module test1( output logic y, input logic a,b,c,d ); 

that implements the following K-map:

c,d 00 01 11 10 01 1 11| 0 | 0 | 0 | 10 0 1 1 1 c,d 00 01 11 10 01 1 11| 0 | 0 | 0 | 10 0 1 1 1