Question: verilog code and testbench code please b. Implement a 4-Bit Subtractor by instantiating your 1-Bit Full Adder module as many times as necessary. Use structural

verilog code and testbench code please b. Implement a 4-Bit Subtractor

verilog code and testbench code please

b. Implement a 4-Bit Subtractor by instantiating your 1-Bit Full Adder module as many times as necessary. Use structural design approach and explicit association. Test it by writing an appropriate testbench

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