Verilog for SRAMs. Using the RAM primitive below, write the Verilog to implement the following: (a) a memory of eight bit-sliced arrays, each with 1024 16-bit words. (b) a memory of 16 banked arrays, each with 152 128-bit words. Only the needed bank should be activated.

RAM primitive:

reg [15:0] mem [0:127];

reg [15:0] rd_data;

always @(posedge clk) begin

if (wr_en == 1b1) begin

mem[wr_addr] <= #1 wr_data;

end

rd_data <= #1 mem[rd_addr];

end