Building and testing basic combinational circuits

Description: Build and test the following circuits using gate$-$level modeling in Verilog HDL$.$

$1.2$x$1$ multiplexer. It takes three inputs: x$,$ y and z and produces one output o u t equals open curly brackets table attributes columnalign left end attributes row cell x comma space i f space z equals $0$ end cell row cell y comma space i f space z equals $1$ end cell end table close. Create a truth table, map, boolean equation for the output function, logic diagram, and Verilog gate$-$level module. Test it with all input combinations.

$2.1-$bit half$-$adder. It adds two bits and produces a sum and a carry output. Create a truth table, maps, boolean equations for the output functions, logic diagram, and Verilog gate$-$level module. Test it with all input combinations.

$3.3-$bit two's complementer $($a circuit that computes the two's complement of a $3-$bit binary number$).$ Use two's complement negation by inverting all bits and adding $1.$ Impement adding $1$ by cascading $3$ half adders. Draw the logic diagram $($with block$-$level half$-$adders$)$ and create a Verilog gate$-$level module using the instances of the half$-$adder module created in item $2.$ Use Verilog vectors $($multiple bit variables$)$ for the inputs$/$outputs$.$ Test the circuit with all input combinatons and show the results both in binary and signed decimal format.

$4.3-$bit two's complementer $($a circuit that computes the two's complement of a $3-$bit binary number$)$ implemented with boolean functions derived directly from the truth table. Create a truth table, maps, boolean equations for the output functions, logic diagam, and Verilog gate$-$level module. Use Verilog vectors $($multiple bit variables$)$ for the inputs$/$outputs$.$ Test it with all input combinations and show the results both in binary and signed decimal format.

PLEASE, Verilog code gate$-$level needed for all circuits.