Verilog HDL

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Design #4 Part A Design a digital system that will output four different code sequences on an output line SIG. The output sequence is determined by the mode control lines MO and M MO M1 SIG 1001 0110 1010 The output SIG is a continuous stream of valid sequences based on M0, MI as long as the control signal GO is asserted. In addition, an output signal SYNC is produced for one clock cycle simultaneous with the first bit of each sequence. Once a sequence is started it is completed and then a new sequence is started based on M0, M1 if G0 is still asserted. SIG is not asserted if G0 is not asserted. Assume all signals are asserted high. PARTEB Design a sequence detector with CLK, SYNC and SIG that will detect the sequence 0110 on SIG. If the sequence is detected the output SEQ is asserted. Simulate and verify the correct operation of both systems