(Verilog language)

This code is supposed to function as 5-bit multiplier and give me 10-bits output to use it in other functions, but it only gives a 1 bit output, how can I make the output be in 10-bits binary form?

mul5b.v Microsoft Visual Studio Edit View Project Debug Team Tools neuron.v:15: neuron.v:15: warning: Port 3 (out) of MUL 2b expects 10 bits, got 1. : Padding (signed) 9 high bits of the port : Padding 3 high bits of the port : Padding 3 high bits of the port. : Padding (signed) 4 high bits of the port. neuron.v:17: warning: Port 1 (a) of FULL_ADDER_Sb expects 4 bits, got 1. neuron.v:17: neuron.v:17: warning: Port 2 (b) of FULL_ADDER Sb expects 4 bits, got 1. tb neuron.v neuron_xor.v I // 5-bit Multiplier module 3 module MUL_5b(a, b, out); neuron.v:17: neuron.v:17: warning: Port 4 (s) of FULL_ADDER_5b expects 5 bits, got 1. neuron.v:17: input signed [4:0) a :\Users Wosenali\Desktop\EE3e312017xxxx> iveri log -o tb-neuron falb.v faSb. neuron.v:14: error: Unknown module type: MUL_5b neuron.v:15: error: Unknown module type: MUL Sb 3 error(s) during elaboration. These modules were missing: MUL_5b referenced 2 times. assign out -(a"b) ue 12 endmodule :\Users\MosenaliVDesktop\EE30312017XXXX>verilog-o tb-neuron falb.v fasb neuron.v:14: warning: Port 3 (out) of MUL_5b expects 10 bits, got 1. neuron.v:14: neuron.v:15: warning: Port 3 (out) of MUL_5b expects 10 bits, got 1. : Padding (signed) 9 high bits of the port. : Padding (signed) 9 high bits of the port. : Padding 3 high bits of the port : Padding 3 high bits of the port. neuron.v:15: neuron.v:17: warning: Port 1 (a) of FULL_ADDER_5b expects 4 bits, got 1. neuron.v:17: euron.v:17: warning: Port 2 (b) of FULL ADDER_5b expects 4 bits, got 1 euron.v:17: neuron.v:17: warning: Port 4 (s) of FULL ADDER_5b expects 5 bits, got 1 uron.v:17: : Padding(signed) 4 high bits of the port C: lUsers Wosenali \Desktop LEE30312017x