please send it google drive send screen here and send a rar file in google drive link and i will upvote you directly

Q1: Given the following Combinational circuit, Use Verilog HDL on Quartus tool to IO I 12 13 4 to 1 MUX Si So 2 to 1 MUX Output S2 14 Is 16 I 4 to 1 MUX Si So 1. Write a Verilog HDL code to describe the module mux4x1 // this module name must be your last name 2. Write a Verilog HDL code to describe the module mux2x1// this module name must be your first name 3. Write a Verilog HDL code to describe the whole system structurally from its subsystems // this module name must be your university number Q2: Problem: Design and Simulation of 8-bit ALU Design an 8-bit ALU circuit that receives two 8-bit input numbers X 17:0) and Y [7:0), and produces a 8-bit output 2 [7:01, an output carry Cout, an overflow flag ov, and Zero flag. The circuit Implements the following 12 functions based on a 3-bit control input [3:01: Code Function 000 Addition:2X+Y 001 Subtraction: 2-X-Y 010 Reminder: 2=X&Y 011 Bitwise AND: 2 X&Y 100 Bitwise OR: 2X1Y 101 Concatenate: 2X(3:0) Y (3:01 110 Equality: ZerowXY 111 Less than: Cout-X