Verilog problem - Using the the following code, create expandable 2(two)BitComparator, along with its testbench to exhaustively test it, then create make an 8(eight)Compatator with the expandable 2(two)BitComparator.

Requirements:

1) Done in behaviroral dataflow modeling

2) Port must be correct because the testbench I will test this 8(eight)Compator will start with the following code

module two bit comparator (A, B,LT, EQU, GT); input 1:0 A,B; output reg LT EQU GT; always a CA,B) begin CCA 1 & 01 &! 1 & 1 &A 01 & EQU 01 &! end endmodule [0]))