VHDL Code for entities:

Logic circuit design:

PROBLEM: come up with the logic for the alu_src and alu_op signals (can be in the form of VHDL code, a truth table, or equations)

You will begin to implement a CPU with the ISA described here, which you can also find from the Resources page. When you have finished part one, your cpu will support the following instructions: add add immediate subtract - subtract immediate and or To complete part one, you will need to create two components The sign_extend component takes a four-bit signed number and extends it to a sixteen-bit signed number. For example: enti "0011"-> "0000000000000011" The control component takes the opcode from the instruction input and generates two signals The alu src signal controls a mux which selects whether the second input of the ALU is a register value (O') or a sign-extended immediate value (1). . The alu_op signal determines which operation the ALU should perform based on the opcode value. end ent You will begin to implement a CPU with the ISA described here, which you can also find from the Resources page. When you have finished part one, your cpu will support the following instructions: add add immediate subtract - subtract immediate and or To complete part one, you will need to create two components The sign_extend component takes a four-bit signed number and extends it to a sixteen-bit signed number. For example: enti "0011"-> "0000000000000011" The control component takes the opcode from the instruction input and generates two signals The alu src signal controls a mux which selects whether the second input of the ALU is a register value (O') or a sign-extended immediate value (1). . The alu_op signal determines which operation the ALU should perform based on the opcode value. end ent