(VHDL MODELSIM) Runing the code below in ModelSim gives the error below. Not sure what the problem is or how to fix it any suggestions would really help.

ERROR MESSAGE:

lasses ECE37 Mabs/Lai b3lmodelsimlelu, whd LI IEEE 2 USE IEEE STD LOGIC 1164. all ieee numeric std. all 5 entity elu is generi ISIZE positive 5: 0SI2E positive 10 in std logic vector ISIZE 1 downto 0 por in std logic 10 out atd logic vector [0 l downto 0 SIZE 12 end entity elu 13 14 architecture dataflow of elu is SIGMAL zero std logic vector OSIZE ISIZE 1 dourto 01 15 16 SIGITAL s bit. std logic vector OSIZE T312E l domto 0 18 begin 19 --Setting up initial bus 20 s it others A (ISI2E L)) 22 others (ISIZE 1 dormto 0