VHDL programming

Task 4: a. Name the type of state machine illustrated by the state machine shown in Figure 2. Write a VHDL program using a single process for the same using the behavioural style of modelling. Assume the state machine has an asynchronous active low reset input driving the state to St-A and it is sensitive to the positive clock edge. (20 Marks) P=0 'P=1 State2 Statel A-101 A=111 P=1 P=0 P=1 State4 State3 P=0 A=011 P=0 A=000 P=1 Figure 2