VHDL Question

Please answer the question fully.

Design a 32 bit Adder Subtractor system, using hierarchical look-ahead techniques. Do this by designing a four bit Adder. Subtractor, and a four bit look-ahead unit. The final system will then require 8 of the four-bit Adder. Subtractor unites plus an appropriate number of the look-ahead unites. The inputs to the system are: A_Bus - 32 bit: value (two's complement) B_Bus - 32 bit value (two's complement) ADD - Add control line: perform addition when high CBIN - Carry (for addition) or Borrow (for subtraction) The outputs are: F_Bus - 32 bit value as result CBOUT - Carry out (Addition) or Borrow out (subtraction) The entity statement is: entity ADD_SUB is generic (DLY: TIME: = 2 ns): port (A_BUS: in STD_LOGIC_VECTOR (31 downto 0): B_BUS: in STD_LOGIC_VECTOR (31 downto 0): ADD: in STD_LOGIC: CBIN: in STD_LOGIC: F_BUS: out STD_LOGIC_VECTOR (31 downto 0): CBOUT: out STD_LOGIC): end entity ADD_SUB: A test bench will be provided. Your task is to come up with an architecture body (two, really) that implements the appropriate logic equations for the system. The design is to be done in a structural fashion