We have a Register File (RF) with 64 4-bit registers (and therefore has 256 flip-flops in order to be implemented). Inside of the RF there will be a decoder for generating the load enables for the registers. Draw the abstraction of this decoder and give names to the input and output signals indicating their purpose. You don't have to draw every single signal; if there is a lot repetition you can show just enough to make a clear pattern. Don't forget that there are times when we might not want any load enable to be asserted; make sure your answer accounts for this.