We have the following program segment executed on a three stage $($I$,$ E$.$ D$)$ RISC pipeline. The pipeline allows two simultaneous memory accesses.

$100$ LOAD R$1.$ X

$101$ LOAD R$2.$ Y

$102$ INC R$1(2)$

$103$ DEC R$2(2)$

$104$ BRANCH $107-$

$105$ ADD R$1,5$

$106$ SUB R$2,2$

$107$ STORE R$2,$ Z$.$

# Load from Address X

# Load from Address Y

# Increment R$1$

# Decrement R$2$

# Branch to Address $107$

# Add $5$ to R$1$

# Subtract $2$ from R$2$

# Store R$2$ at Address Z

Using delayed branch in pipeline operation in the above program, draw the pipeline timing diagrams:

i$-$using NOOPs

after rearranging the instructions $($optimized delayed branch$)9$

Calculate the clock cycles required to execute the above program in each case.