Question: We have the following program segment executed on a three stage ( I , E , D ) RISC pipeline. The pipeline allows two simultaneous
We have the following program segment executed on a three stage I E D RISC pipeline. The pipeline allows two simultaneous memory accesses.
LOAD R X #Load from Address X
LOAD R Y #Load from Address Y
INC R #Increment R
DEC R #Decrement R
BRANCH #Branch to Address
ADD R #Add to R
SUB R #Subtract from R
STORE R Z #Store R at Address Z
Using delayed branch in pipeline operation in the above program, draw the pipeline timing diagrams:
i using NOOPS
ii after rearranging the instructions optimized delayed branch
Step by Step Solution
There are 3 Steps involved in it
1 Expert Approved Answer
Step: 1 Unlock
Question Has Been Solved by an Expert!
Get step-by-step solutions from verified subject matter experts
Step: 2 Unlock
Step: 3 Unlock
