we have to write 3 to 8 decoder in vhdl using 2 to 4 decoder already implemented and I provided the vhdl program but need help implementing 3 to 8 decoder in vhdl

-use IEEE NUMERIC_STD.ALL; Uncomment the following library declaration if instantiating any Xilinx primitives in this code. library UNISIM; -use UNISIM.VComponents.alli entity decode_2to4 is Port (I in STD LOGIC VECTOR (1 downto 0) Y out STD LOGIC VECTOR (3 downto 0) EN : in STD LOGIC) end decode 2to4; architecture decode 2to4_arch of decode_2to4 is egin process (I, EN) begin if (EN-'1') then active high enable pin Y (0) ignored due to previous errors. Ln 47