We need to design a cache with cache size of 128K bytes, block (line) size of 8 words, and word size of 4 bytes. Consider a computer with 64-bit physical address. The cache is addressed by physical address. 1.) (20 pts) Determine the tag array size (in bytes) for direct-mapped cache implementations 2.) (20 pts) Determine the tag array size (in bytes) for 16-way set-associative cache implementations. 3.) (20 pts) Determine the tag array size (in bytes) for fully associative cache implementations