What do the control signals do? explain for each in the table

Below is a copy of the LEGv8 single-cycle data path design. Add 2x 4- ALU Add result Shift left 2 Reg2Loc Branch MemRead Instruction (31-21) Control MemoReg ALUOP Meminte ALUSIC Reg Write Instruction (9-5) Read Instruction (20-1610 register 1 Read Read data 1 register 2 Write Read Instruction (4-0) Write data Registers PC Read address Zero ALU ALU Instruction (31-0) Instruction memory Address data Read result register data 2 2x Write Data data memory Instruction (31-0) 32 64 Sign- extend ALU control Instruction (31-21] What do the following control signals do? If the signal is a bus, explain all the individual signals. ALHOR ALUSCE Branch MemBead MenteReg MenWrite Reg2Loc RegWrite Zero