What is the AMAT for a processor with a $2$ns clock cycle time, a miss penalty of $25$ clock cycles, a miss rate of $0\mathrm{.}05$ misses per instruction, and a cache access time $($including hit detection$)$ of $2$ clock cycles? The read and write miss penalties are the same and you do not have to consider write stalls.

Question $6$ options:

$5$ clock cycles

$2\mathrm{.}5$ clock cycles

$3\mathrm{.}25$ clock cycles

$2$ clock cycles