Question: what is the design error verilog module and_comb_reset (a, b, reset , out ) ; input a b, reset ; output reg out ; always

what is the design error verilog module and_comb_reset (a, b, reset

what is the design error verilog

module and_comb_reset (a, b, reset , out ) ; input a b, reset ; output reg out ; always @(a, b) begin out = a & b; end always @( reset ) begin if (reset == 1 ' bi ) out = 1 ) be ; end endmodule

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