What is the proper VHDL declaration code for a component that functions as an OR gate?

Select one:

a$.$

COMPONENT or$\_$gate IS

PORT $($ in$1,$ in $2$: IN BIT;

$01$ : OUT BIT$)$;

END COMPONENT;

b$.$

COMPONENT or IS

PORT $($ in$1,$ in $2$: IN BIT;

$01,02$ : OUT BIT$)$:

END COMPONENT;

c$.$ none of them

d$.$

COMPONENT or$\_$gate IS

PORT $($in$1,$ in $2$: IN BIT;

$01,02$: OUT BIT$)$;

END COMPONENT;

e$.$

COMPONENT or IS

PORT $($ in$1,$ in $1$: IN BIT;

$01$: OUT BIT$)$;

END COMPONENT;