modify the VHDL code as it is says below, and picture of the RLT simulation

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LIBRARY ieee; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL;

ENTITY shifter_tb IS END ENTITY shifter_tb;

ARCHITECTURE stimulus OF shifter_tb IS

-- Component declaration for the DUT COMPONENT shifter PORT ( input: IN UNSIGNED (7 DOWNTO 0); shift_cntrl : IN UNSIGNED (1 DOWNTO 0); shift_out : OUT UNSIGNED (15 DOWNTO 0) ); END COMPONENT shifter;

-- Signals to connect to DUT SIGNAL input : UNSIGNED (7 DOWNTO 0); SIGNAL shift_cntrl : UNSIGNED (1 DOWNTO 0) := "00"; SIGNAL shift_out : UNSIGNED (15 DOWNTO 0);

BEGIN -- beginning of architecture body

-- instantiate unit under test (mult4x4) shifter1 : shifter PORT MAP ( input => input, shift_cntrl => shift_cntrl, shift_out => shift_out );

-- Fix data input to hex value "F4" input Write the source code for a 8-bit to 16-bit left shifter using the IF-THEN sequential statement. Use the following information as a guide: a. The multiplexer has one 8-bit data input, a control line and a 16-bit output. b. Describe the following behavior o The default shift out value is all zeros, if all bits of the shift out are not assigned a value for every if then else case, unwanted latches will result. i. look for a warning messages about latches, you do not want any 1. Warning (10631): VHDL Process Statement warning at Check your message window to see if you are creatin latches latches inferred shifter.vhd(18): inferring latch(es) for signal or variable "shift out", which holds its previous value in one or more paths through the process ii. To elminate the above message you must assign shift out a value in everv if-then-else case or provide a default value at the beginning of the process such as: 1. shift out