Question: Which expression does the output Out evaluate to in the following SystemVerilog Snippet? module hw 4 _ q 1 ( input logic A , input

Which expression does the output "Out" evaluate to in the following SystemVerilog
Snippet?
module hw4_q1(input logic A,
input logic B,
input logic C,
output logic Out);
logic w, w1, c1,c2;
not n(w,B);
not n1(w1,A);
and , we);
and a1(c2,B,w1);
or oe(Out,c1,c2);
endmodule
F=A?,B,C(0,1,4,5)
F=A?,B,C(0,1,2,3)
F=A?,B,C(2,3,4,5)
F=A?,B,C(4,5,6,7)
None of the others
Which expression does the output "Out" evaluate to in the following

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