Consider the following SystemVerilog module: module foo (input logic a,b, output logic c); assign ca; .00 on always_comb if(b) c-a&b; endmodule What are the problems with this module? Select one: a. No begin/end in the always statement. b. There should not be a semicolon at the end of the module line and there are no internal wires declared. C. There is no delay information. d. The if-statement doesn't contain a begin/end. e.c is assigned with blocking assignment statement and there is no type specified for input b f. The assign statement uses a tilde instead of an explanation point to complement a g.c is double driven, the always block has no default assignment for c