With explanation please!

l. Consider this code, which has a RAw hazard involving R3 that can be resolved without stalling using data forwarding: DADDI R3, R1 12 DADD RI, R0, R1 DADD R5, R6, R3 a) What data forwarding hardware must be added to the variation 1 MIPs to handle this code without stalling? Show the required hardware by drawing it in a different color on a diagram of the variation 1 MIPS pipeline. (You do not have to include all the details of the standard pipeline, but give enough that we can see clearly how the new hardware fits in.) b) The data is being forwarded from where to where? Be as specific as you can, using the usual register transfer level notation. Also, what Boolean expression is used to decide whether to activate the path that forwards the data in a given clock cycle? l. Consider this code, which has a RAw hazard involving R3 that can be resolved without stalling using data forwarding: DADDI R3, R1 12 DADD RI, R0, R1 DADD R5, R6, R3 a) What data forwarding hardware must be added to the variation 1 MIPs to handle this code without stalling? Show the required hardware by drawing it in a different color on a diagram of the variation 1 MIPS pipeline. (You do not have to include all the details of the standard pipeline, but give enough that we can see clearly how the new hardware fits in.) b) The data is being forwarded from where to where? Be as specific as you can, using the usual register transfer level notation. Also, what Boolean expression is used to decide whether to activate the path that forwards the data in a given clock cycle